Exemplary embodiments relate to a pipelined analog-to-digital converter.
An image system such as HDTV may necessitate an high-performance analog-to-digital converter (hereinafter, referred to as ADC) which provides a high resolution of 10 bits to 12 bits and a high sampling speed of hundreds MHz. Among various ADC structures, a pipeline structure may have been used to satisfy high-speed signal processing and high-resolution conditions.
A typical pipelined ADC may have such a problem that its realization area increases according to an increase in a resolution of a lower conversion stage. Such a problem may be caused due to a decoder whose realization area increases in proportion to a bit number of a digital code output from a conversion stage at a digital correction operation. In particular, in case of the typical pipelined ADC, its logic complexity at the digital correction operation may increase because a conversion region of the conversion stage is used as an even-numbered period.